Magnetoresistive Random Access Memory (MRAM) is a non-volatile memory technology that uses magnetic elements. MRAM operation is well known, and can be briefly explained using the example of a commonly used variety of MRAM, a Spin Transfer Torque MRAM (STT-MRAM). A STT-MRAM uses electrons that become spin-polarized as the electrons pass through a thin film (spin filter).
FIG. 1 illustrates a conventional STT-MRAM bit cell 100. The STT-MRAM bit cell 100 includes magnetic tunnel junction (MTJ) storage element 105 (also referred to as “MTJ stack” or “MTJ cell”), transistor 101, bit line 102 and word line 103. MTJ cell 105 is formed, for example, from pinned layer 124 and free layer 120, each of which can hold a magnetic moment or polarization, separated by insulating tunneling barrier layer 122.
Where the design of MTJ cell 105 is that of an in-plane MTJs, an anti-ferromagnetic (AFM) layer and a cap layer (not shown) are used in MTJ cell 105. The AFM layer is used to pin the magnetic moment of the pinned layer of an in-plane MTJ. The cap layer is used as a buffer layer between the MTJ and metal interconnects. Where MTJ cell 105 is designed as a perpendicular MTJ, pinned layer 124 is present but an AFM layer is not included.
The polarization of the free layer can be reversed by applying current in a specific direction such that the polarity of the pinned layer and the free layer are either substantially aligned or opposite. The resistance of the electrical path through the MTJ varies depending on the alignment of the polarizations of the pinned and free layers. This variation in resistance can be used to program and read STT-MRAM bit cell 100, as is known. STT-MRAM bit cell 100 also includes circuit elements, source line 104, sense amplifier 108, read/write circuitry 106 and bit line reference 107. Those skilled in the art will appreciate the operation and construction of STT-MRAM bit cell 100 as known in the art.
As seen from the above example, the formation of a conventional STT-MRAM bit cell involves integration of the various above-described components on a circuit board or semiconductor package. More specifically, memory or storage elements (e.g., MTJ bit cell 105) must be integrated with various other circuit elements (generally referred to herein, as, “logic elements”) such as, passive components, metal wires, transistors, logic gates, etc. In general, such integration requires process compatibility between the memory elements and the logic elements.
However, it is well known that semiconductor technology scaling is not uniform across the various components of integrated circuits. For example, with regard to MRAM formation, metal wire width and height of vertical interconnect access (commonly known as “via”) are seen to scale by about 70% from one generation to the next. On the other hand, aspects such as height of MTJ bit cells, cap layer thickness, etc., fail to scale at comparable pace.
Applicant's commonly owned US Patent Application to Li et al. (US Patent Publication 2012/0032287, entitled “MRAM Device and Integration Techniques Compatible with Logic Integration,” currently pending and hereinafter referred to as “Li”), discloses various techniques for integration of a logic process (i.e., pertaining to formation of logic elements) with a process of forming MRAM device elements such as MTJ bit cells.
With reference to FIG. 2, a memory device similar to one of Li's disclosed embodiments is illustrated. More particularly, FIG. 2 illustrates a cross-sectional view of memory device 200, which reflects an embodiment of Li, with reference numerals modified and/or added for the purposes of this disclosure. The following nomenclature is applicable to FIG. 2. Elements of memory device 200 are illustrated in three layers identified as “x−1,” “x,” and “x+1,” corresponding to inter metal dielectric (IMD) layers IMDx−1, IMDx, and IMDx+1. The same suffix to identify an IMD layer is also added to metal/via elements present in the corresponding IMD layer. The illustrated elements are shown to be partitioned as “logic” elements, which are juxtaposed with “MTJ” elements.
In more detail, the logic elements are representatively illustrated as vias and metal lines following the above notation, with vias V′x+1 and V′x in layers x+1 and x respectively, and metal lines M′x and M′x−1 in layers x and x−1 respectively.
On the MTJ side, bit cell MTJ 202 is illustrated in layer x, with top electrode (TE) 204, and bottom electrode (BE) 206. Metal line Mx may be coupled to TE 204 in layer x, which can be further coupled to via Vx+1 in layer x+1, through the optional use of a top via top_Vx in layer x. Cap layer Cap3x in layer x is an optional feature for isolation and formation of a metal island for metal line Mx. BE 206 may be coupled to metal line Mx−1 in layer x−1 through via Vx.
Common to both the logic side and MTJ side elements are IMD layers IMDx−1, IMDx, and IMDx+1 in each of the layers x−1, x, and x+1, respectively. These IMD layers are separated by one or more cap layers in the depicted embodiment. The insulating cap layers are diffusion barrier layers for the metal lines and may be formed from insulators such as SiC, SiN film, etc. More specifically, one or more bottom cap layers, bottom-caps 1-2, separate IMD layers, IMDx−1 and IMDx+1, whereas, one or more top cap layers, top-caps 1-2, separate IMD layers IMDx and IMDx+1.
While the memory device 200 of FIG. 2 depicts robust and effective integration of the logic and MTJ side elements in Li for current technologies, technological advances place ever increasing restrictions on the maximum available height in each of the layers x−1, x, and x+1. The height of a layer may be viewed as the separation between cap layers bounding the layers. For example, the height of layer x may be viewed in terms of the distance between bottom cap layers, bottom-caps 1-2, and top cap layers, top-caps 1-2. As future technologies evolve into 20 nm, 16 nm, 10 nm arenas, and beyond, the height of layer x, for example, may shrink to reach dimensions which are so small that the height of layer x will barely be sufficient to accommodate via V′x and metal M′x on the logic side. This is because, as noted above, metal lines and vias can scale relatively rapidly with evolving technologies. However, MRAM technology is unlikely to evolve at the same rate. In other words, with evolving technologies, it will be highly challenging to accommodate the currently illustrated configuration for the MTJ side in layer x, if the height of layer x reaches dimensions which are barely sufficient to accommodate via V′x.
Accordingly, with evolving technology and shrinking device sizes, MTJ 202 may extrude into the metal island Mx. Further, the metal island Mx may need to be thinned, to the point where metal island Mx may effectively become non-existent. While Li discloses embodiments where components on the MTJ side in layer x may be lowered, such that BE 206 may be sunk deeper, for example, into bottom-cap 2, this may lead to increased stress on the remaining bottom cap layer, bottom-cap 1, as the technology evolves. On the other hand, elevating the position of the components on the MTJ side may begin intruding into the top, x+1 layer.
Accordingly, for numerous reasons, the current approaches for MRAM and logic integration in semiconductor devices may not be viable for future technologies, as device sizes continue to shrink.